MRAM|SSD|Speicher News und Infos

Within a short time, embedded designers will face major challenges associated with embedded memory at or around the 45-nanometer technology node. Industry leaders have already declared that conventional SRAM, flash and DRAM will encounter scalability and endurance issues at those feature sizes.

Consequently, embedded memory management not only takes on new meaning but also faces different design perspectives and associated challenges. That's because memory chip makers are altering once-stable architectures and technologies to comply with scalability and endurance demands. To fend off those inevitabilities, conventional memory vendors are attempting to shoehorn more circuitry into already well-altered and crowded architectures, while newcomers try different technology routes.

Meanwhile, microprocessor makers are pushing for increasingly higher performance. These newer, more powerful microprocessors with embedded memory management units (MMUs) will pose their own set of design issues as they confront conventional memory problems at or around 45 nm. Those basic issues may be exacerbated by such newer memory technologies as first-generation magnetoresistive RAM (MRAM) and phase-change RAM (PRAM).

MMUs are expected to undergo a metamorphosis into more complex structures to meet the demands of highly advanced systems-on-chip (SoCs) populated with multiple embedded processors. For example, recent research has led to dynamic two-level memory management, said to be faster than software-based memory management.
full eetimes.com